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M54HC74
RAD HARD DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
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HIGH SPEED: fMAX = 67MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 74 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9203-050
DILC-14
FPC-14
ORDER CODES
PACKAGE DILC FPC FM M54HC74D M54HC74K EM M54HC74D1 M54HC74K1
DESCRIPTION The M54HC74 is an high speed CMOS DUAL D TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology.
A signal on the D INPUT is transferred on the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low on the appropriate input. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION
June 2004
Rev. 1
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Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N 1,13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 SYMBOL 1CLR, 2CLR 1D, 2D 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW-to-HIGH, Edge-Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage
Table 2: Truth Table
INPUTS CLR L H L H H H
X : Don't Care
OUTPUTS FUNCTION D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn CLEAR PRESET ---------NO CHANGE
PR H L L H H H
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Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Table 3: Absolute Maximum Ratings
Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 50 300 -65 to +150 265 Unit V V V mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
Table 4: Recommended Operating Conditions
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns
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Table 5: DC Specifications
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 2 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 20 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 40 A A V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
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Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25C Min. Typ. 30 8 7 48 16 13 51 17 15 21 63 67 18 6 6 21 7 6 15 4 3 Max. 75 15 13 150 30 26 150 30 26 5 25 30 75 15 13 75 15 13 75 15 13 0 0 0 25 5 4 95 19 16 95 19 16 95 19 16 0 0 0 30 6 5 Value -40 to 85C Min. Max. 95 19 16 190 38 32 190 38 32 4.2 21 25 110 22 19 110 22 19 110 22 19 0 0 0 35 7 6 -55 to 125C Min. Max. 110 22 19 225 45 38 225 45 38 ns Unit
tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CK - Q, Q) tPLH tPHL Propagation Delay Time (CLR, PR Q, Q) fMAX Maximum Clock Frequency Minimum Pulse Width (CK) Minimum Pulse Width (CLR, PR) Minimum Set-up Time Minimum Hold Time Minimum Removal Time (CLR, PR to CK)
ns
ns
6.2 31 37
MHz
tW(H) tW(L) tW(L)
ns
ns
ts
ns
th
ns
tREM
0 0 0
ns
Table 7: Capacitive Characteristics
Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25C Min. Typ. 5 34 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/ FLOP)
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Figure 4: Test Circuit
CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
Figure 5: Waveform - nCK To nQ, nQ Propagation Delay Times, and To nCK Setup And Hold Times, nCK Minimum Pulse Width, Maximum nCK Frequency (f=1MHz; 50% duty cycle)
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Figure 6: Waveform - nQ , nQ TO CLR, PR Propagation Delay Times, Minimum Pulse Width (nCLR and nPR) (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Minimum Pulse Width (nCLR and nPR), Minimum Removal Time (nCLR and nPR TO nCK) (f=1MHz; 50% duty cycle)
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Figure 8: Waveform - Minimum Pulse Width (nCLR, nPR, nCK) (f=1MHz; 50% duty cycle)
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DILC-14 MECHANICAL DATA
mm. DIM. MIN. A a1 a2 B b b1 D E e e1 e2 F I K L 10.90 1.14 1.27 15.11 7.62 7.11 2.1 3.00 0.63 1.82 0.40 0.20 18.79 7.36 0.88 2.03 0.45 0.254 19.00 7.62 2.54 15.24 7.87 15.37 8.12 7.75 3.70 12.1 1.5 0.429 0.045 0.050 0.595 0.300 0.280 TYP MAX. 2.54 3.70 1.14 2.39 0.50 0.30 19.20 7.87 MIN. 0.083 0.118 0.025 0.072 0.016 0.008 0.740 0.290 0.035 0.080 0.018 0.010 0.748 0.300 0.100 0.600 0.310 0.605 0.320 0.305 0.146 0.476 0.059 TYP. MAX. 0.100 0.146 0.045 0.094 0.020 0.012 0.756 0.310 inch
0016173H
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FPC-14 MECHANICAL DATA
mm. DIM. MIN. A B C D E F G H L M N 18.75 0.38 4.31 0.38 6.75 9.76 1.49 0.10 7.50 0.127 7.62 1.27 0.43 6.0 22.0 0.738 0.015 0.170 0.48 0.015 TYP 6.91 9.95 MAX. 7.06 10.14 1.95 0.15 7.75 MIN. 0.266 0.384 0.059 0.004 0.295 0.005 0.300 0.050 0.017 0.236 0.866 0.019 TYP. 0.272 0.392 MAX. 0.278 0.399 0.077 0.006 0.305 inch
F
G
D
H
14
8
A
N
L
1
7
H
E
B
M
C
016029E
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Table 8: Revision History
Date 01-Jun-2004 Revision 1 First Release Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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